The Graduate School Design and Analysis of Heterogeneous Networks for Chip-multiprocessors

Rarely has there been as challenging and exciting a time for research in computer architecture as now. While, the proverbial Moore’s law has consistently helped architects integrate more and more silicon transistors in a single die, device constraints of power, heat, and reliability has forced the computer industry to shift focus from single processor core performance to instantiating multiple processor cores on a chip. In this quest for integrating a large number of cores on a single chip, one particular area of computer architecture that has come into prominence is the interconnection network on a chip (also called network-on-chip or NoC). NoCs seek to provide a scalable, energy-efficient and high-bandwidth communication substrate for future multi-core and many-core architectures an aspect that critically dictates future chip designs. Most of the prior research in NoC has focussed on optimizing the NoC considering it as a homogeneous system i.e. all optimizations proposed, equally affect all the components in the NoC substrate. However, this dissertation demonstrates that the resources in the NoC (precisely, buffers and links) are not always equally utilized, and that not all applications demand similar resources from the underlying interconnection substrate. Hence, this dissertation argues that better and smarter NoCs can be architected by considering the inherent heterogeneity in NoCs from both the network architecture perspective and from the applications’ perspective. Further, considering the fact that future multicores and systems-onchip architectures will have heterogeneous cores and compute engines, and host diverse applications, it is also inevitable that not all components will demand similar responses from the NoC and neither will these compute engines stress the NoC uniformly. Thus, it is compelling to think of heterogeneous NoCs for such heterogeneous systems. To this end, this dissertation argues in favor of NoCs that factor heterogeneity as a first-order design objective while architecting them for future multi-core systems.